1. Field of the Invention
This invention relates to solid state mass memory systems. Still more particularly, this invention relates to adaptive solid state memory systems which employ stacked WSI reconfigurable memory wafers controlled by an off-wafer memory system control means.
2. Description of the Prior Art
Conventional mass memory systems can be conveniently divided into two groups, those involving magnetic media and those employing transistor technolgoy. Included within the magnetic media devices are the multitude of tape and disc drive memory systems. While these devices are relatively inexpensive in terms of a cost-per-bit criterion, the systems tend to the bulky, slow, and consume relatively high levels of power in their operation. Also included within the magnetic media magnetic systems are the magnetic bubble memory systems. Such systems represent an importatnt reduction in the size of the device but are still relatively high in power, limited in operating temperature rate, and slow in access time. All of the magnetic media memory systems posssess the important advantage of nonvolatility; that is, upon termination of power to the memory system, the data within the system is not lost and may be retrieved upon reapplication of power to the memory system.
The transistor implemented mass memory systems include MOS, bipolar, and CCD mass memory systems. These transistor implemented mass memory systems are much faster than those employing magnetic media.
Indeed, the bipolar mass memory systems are among the faster memories available today. Nevertheless, these memory systems are substantially more costly in terms of a cost per bit of storage criterion than are the magnetic media mass memorues; and perhaps most significantly, the transistor implemented mass memories are volatile. In other words, an interruption of power to these transistor implemented mass memories will cause a catastrophic effect in that none of the data in the transistor memory will be retained for retrieval upon a reapplication of power to the transistorized mass memory system. By way of a quick comparison, the adaptive wafer scale integration (AWSI) solid state memory system of this invention which employs nonvolatile MNOS transistor technology media memory systems in terms of cost per bit of storage, is nonvolatile, is highly reliable due to its adaptive reconfigurability, and has an access speed intermediate to the magnetic media mass memories and the other transistor implemented mass memories.
The mass memory system of this invention is based in large part on Metal Nitride Oxide Semiconductor (MNOS) transistor technology for both the nonvolatility of the data within the memory and for the adaptive reconfigurability of the components on the individual memory wafers by which the memory system achieves a very high reliability. The basic operation and method of fabrication for MNOS devices have been known for some time; see, for example, an article by M. H. White and J. R. Cricchi, "Characterization of Thin-Oxide MNOS Memory Transistor," IEEE Trans. Electron Devices, vol. Ed-19, pp. 1280-1288, 1972. In a nutshell, the MNOS transistor is a close relative of the conventional MOS transistor in that the usual layer of gate oxide is replaced by a 400 angstrom layer of silicon nitride over a less than 20 angstrom thick layer of silicon dioxide. The application of a moderately high voltage (approximately 20 volts) to the gate electrode of this transistor causes the thin silicon dioxide layer to become conductive or to permit charge carriers to tunnel through it. Charge carriers may then pass between the silicon substrate and the charge carrier traps located near the silicon nitride-silicon dioxide interface. The presence of trapped charge carriers at this interface modifies the gate voltage which controls passage of charged carriers from source to drain in the conventional operation of the transistor. The MNOS transistor is then said to have an OFF and an ON state, which depends on the concentration and the polarity of the trapped charge carries. These MNOS transistors, when suitably utilized in a circuit, effectively become the means with which electrically-alterable interconnections can be accomplished. The alterable interconnect can be so utilized because the interconnection has a nonvolatile memory for status control such that the state of an interconnected machine is static as if hardwired, yet it is alterable (or adaptive), via control signals from other circuit means.
Some of the most recent developments in adaptive reconfigurability of circuits involving MNOS transistors are represented by U.S. Pat. No. 4,188,670, by Yukun Hsia, issued Feb. 12, 1980, entitled "Associative Interconnection Circuit" and U.S. Ser. No. 954,627, now U.S. Pat. No. 4,254,477, issued Mar. 3, 1981, by Yukun Hsia, entitled "Reconfigurable Memory Circuit." Nevertheless, these references disclose only relatively small scale implementations of these circuits.